spread spectrum frequency timing generator W155 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07147 rev. *a revised september 24, 2001 features ? generates a spread spectrum timing signal (sysclk) and a non-spread signal (usbclk) requires a 14.318-mhz crystal for operation supports mips microprocessor clock frequencies reduces peak emi by as much as 12 db integrated loop filter components cycle-to-cycle jitter = 250 ps (max) operates with a 3.3 or 5.0v power supply spread output is selectable from 10 to 133 mhz test mode supports modulation off (high-z) and spe- cial test input reference frequency guaranteed 45/55 duty cycle packaged in a 16-pin, 300-mil-wide soic (small outline integrated circuit) overview the W155 incorporates the latest advances in pll-based spread spectrum frequency synthesizer technology. by fre- quency modulating the sysclk output with a low-frequency carrier, peak emi can be greatly reduced in a system. use of this technique allows systems to pass increasingly difficult emi testing without resorting to costly shielding or redesign. in a system that uses the W155, not only is emi reduced in the various clock lines, but also in all signals which are synchro- nized to sysclk. therefore, the benefits of using this tech- nique increase with the number of address and data lines in the system. the W155 is specifically targeted toward mips microproces- sor based systems where emi is of particular concern. each device uses a single 14.318-mhz crystal to generate a select- able spread spectrum output and an unmodulated 48-mhz usb output. the spreading function can be disabled by taking the sson# pin high. spread percentage can be selected with the ss% input (see table 2 below). table 1. frequency selection (14.318-mhz reference) fs3 fs2 fs1 fs0 sysclk (output freq.) 0000 133.3 mhz 0001 120 mhz 0010 100 mhz 0 0 1 1 74.77 mhz 0100 70 mhz 0101 66.6 mhz 0110 60 mhz 0111 50 mhz 1000 40 mhz 1 0 0 1 33.33 mhz 1010 30 mhz 1011 25 mhz 1100 20 mhz 1 1 0 1 16.67 mhz 1110 12 mhz 1111 10 mhz table 2. spread percentage selection ss% spread percentage 0? 1.25% 1 ? 3.75% pin configuration test vdd usbclk/ss%* gnd sysclk gnd fs0* sson#^ 16 15 14 13 12 11 10 9 vdd x1 x2 gnd fs3* vdd fs2* fs1* 1 2 3 4 5 6 7 8 W155 [1] note: 1. internal pull-up resistor present on inputs marked with ? * ? and pull-down resistor present on input marked with ? ^ ? .
W155 document #: 38-07147 rev. *a page 2 of 7 pin definitions pin name pin no. pin type pin description usbclk/ ss% 14 i/o usb clock output/modulation width selection input: when an input; if spread spectrum feature is enabled, this pin is used to select the amount of frequency variation on the sysclk output (see table 2 ). wider variations result in greater peak emi reduction. when an output: supplies a non-spread 48-mhz signal for usb support. sysclk 12 o system clock output: frequency is selected per table 1 . spread spectrum feature is controlled by pins 9 & 14. fs0:3 10, 8, 7, 5 i frequency select pins: these pins set the frequency of the signal provided at the sysclk output. sson# 9 i spread spectrum control (active low): pulling this input signal high turns the internal modulating waveform off. this pin has an internal pull-down resistor. x1 2 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as either an external crystal connection, or as an external reference frequency input. x2 3 i crystal connection: if using an external reference, this pin must be left uncon- nected. test 16 i test mode: for normal operation, tie this pin to ground. vdd 1, 6, 15 p power connection: connected to either 3.3v or 5.0v power supply. all vdd pins must be the same voltage level. gnd 4, 11, 13 g ground connection: connect to the common system ground plane.
W155 document #: 38-07147 rev. *a page 3 of 7 functional description i/o pin operation pin 14 is a dual purpose l/o pin. upon power-up each i/o pin acts as a logic input, allowing the determination of assigned device functions. a short time after power-up, the logic state of each pin is latched and each pin then becomes a clock output. this feature reduces device pin count by combining clock outputs with input select pins. an external 10-k ? ? strapping ? resistor is connected between each l/o pin and ground or v dd . connection to ground sets a ? 0 ? bit, connection to v dd sets a ? 1 ? bit. see figure 1 . upon W155 power-up, the first 2 ms of operation is used for input logic selection. during this period, each clock output buff- er is three-stated, allowing the output strapping resistor on each l/o pin to pull the pin and its associated capacitive clock load to either a logic high or low state. at the end of the 2-ms period, the established logic 0 or 1 condition of each l/o pin is then latched. next the output buffer is enabled convert- ing all l/o pins into operating clock outputs. the 2-ms timer starts when v dd reaches 2.0v. the input bits can only be reset by turning v dd off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of the clock outputs is <40 ? (nominal) which is minimally affected by the 10-k ? strap to ground or v dd . as with the se- ries termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v dd should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when each clock output is enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that v dd has stabilized. if v dd has not yet reached full value, output frequency initially may be below target but will increase to target once v dd voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. output buffer configuration clock outputs all clock outputs are designed to drive serial terminated clock lines. the device outputs are cmos-type which provide rail-to-rail output swing. crystal oscillator the device requires one input reference clock to synthesize all output frequencies. the reference clock can be either an ex- ternally generated clock signal or the clock generated by the internal crystal oscillator. when using an external clock signal, pin x1 is used as the clock input and pin x2 is left open. the input threshold voltage of pin x1 is (v dd )/2. the internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins x1 and x2. this forms a parallel resonant crystal oscillator circuit. the device incor- porates the necessary feedback resistor and crystal load ca- pacitors. including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pf. for opti- mum frequency accuracy without the addition of external ca- pacitors, a parallel-resonant mode crystal specifying a load of 20 pf should be used. this will typically yield reference fre- quency accuracies within 100 ppm. to achieve similar accu- racies with a crystal calling for a greater load, external capac- itors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal. power-on reset timer output three-state data latch hold qd W155 v dd clock load r 10 k ? output buffer output low output strapping resistor series termination resistor jumper options figure 1. input logic selection through jumper option
W155 document #: 38-07147 rev. *a page 4 of 7 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 2 . as shown in figure 2 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 3 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is specified in table 2 . figure 3 details the cypress spreading pattern. cypress does offer op- tions with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate values for pin 9. spread spectrum enabled emi reduction spread spectrum non- figure 2. clock harmonic with and without sscg modulation frequency domain representation max min 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 3. typical modulation profile
W155 document #: 38-07147 rev. *a page 5 of 7 absolute maximum ratings [2] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c note: 2. single power supply: the voltage on any input or i/o pin cannot exceed the power pin during power-up. dc electrical characteristics: 0 c < t a < 70 c, v dd = 3.30v10% parameter description test condition min typ max unit i dd supply current 35 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2 ma 50 mv v oh output high voltage i oh = ? 2 ma 3.10 v i ol output low current v ol = 1.5v 80 110 155 ma i oh output high current v oh = 1.5v 80 120 175 ma i il input low current 10 a i ih input high current 10 a c i input capacitance 5 10 pf c l xtal load capacitance 20 pf switching characteristics parameter description test conditions min typ max unit t tlh , t thl output rise and fall time measured at 10% of 90% of v dd 0.8 4.0 ns t tlh, t thl output rise and fall time measured at 0.8v ? 2.0v 0.3 1.0 ns t sym output duty cycle 45 55 % t jcc cycle-to-cycle jitter 250 ps emi emi attenuation 11th harmonic, 25 mhz 10 db ordering information ordering code package name package type W155 g 16-pin plastic soic (300-mil, wide body)
W155 document #: 38-07147 rev. *a page 6 of 7 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 16-pin small outlined integrated circuit (soic, 300 mils, wide body) 0.399 - 0.412 (10.13 - 10.46) 0.285 ? 0.299 (7.42 ? 7.59) 0.40 ? 0.41 (10.16 ? 10.41) 0.189 - 0.196 (4.80 - 4.98) 0.0020 ? 0.015 (0.06 ? 0.38) 0.097 - 0.104 (2.46 - 2.64) 0.014 - 0.019 (0.35 - 0.48) 0.05 (1.27) 0.009 - 0.0125 (0.23 - 0.32) 0.024 - 0.040 (0.61 - 1.02) 5 nom note: all linear dimensions are in inches and parenthetically in millimeters, min. ? max. 16 9 1 8 bsc
W155 document #: 38-07147 rev. *a page 7 of 7 document title: W155 spread spectrum frequency timing generator document number: 38-07147 rev. ecn no. issue date orig. of change description of change ** 110256 12/15/01 szv change from spec number: 38-00785 to 38-07147 *a 122685 12/27/02 rbi added power up requirements to maximum ratings information.
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